Patents
Kathryn holds over 65 patents, reflecting her extensive contributions to semiconductor technology and integrated circuits. Her innovations include advancements in double-gate transistor structures, three-dimensional integrated circuits, and nonvolatile memory devices utilizing semiconductor nanocrystals. These patents highlight her role in pioneering developments that have significantly influenced modern electronics.
Patent list
Nonvolatile Memory Device Using Semiconductor Nanocrystals And Method Of Forming Same
Patent No.: US 8,987,138 B2.
Interconnect Structures With Engineered Dielectrics With Nanocolumnar Porosity
Patent No.: US 8,901,741 B2.
Method Of Forming A Nonvolatile Memory Device Using Semiconductor Nanoparticles
Patent No.: US 7,985,686 B2.
Low Temperature Fusion Bonding With High Surface Energy Using A Wet Chemical Treatment
Patent No.: US 7,566,631 B2.
High-Performance CMOS Devices On Hybrid Crystal Oriented Substrates
Patent No.: US 7,329,923 B2.
Connection Device With Actuating Element For Changing A Conductive State Of A Via
Patent No.: US 7,342,301 B2.
Self-Aligned Planar Double-Gate Process By Self-Aligned Oxidation
Patent No.: US 7,205,185 B2.
Nonvolatile Memory Device Using Semiconductor Nanocrystals And Method Of Forming Same
Patent No.: US 7,045,851 B2.
Method Of Fabricating Silicon Devices On Sapphire With Wafer Bonding At Low Temperature
Patent No.: US 6,911,375 B2.
Three Dimensional CMOS Integrated Circuits Having Device Layers Built On Different Crystal Oriented Wafers
Patent No.: US 6,821,826 B1.
Self-Aligned SOI With Different Crystal Orientation Using Wafer Bonding And SIMOX Processes
Patent No.: US 6,830,962 B1.
Self-Aligned Silicide Process Utilizing Ion Implants For Reduced Silicon Consumption And Control Of The Silicide Formation Temperature And Structure Formed Thereby
Patent No.: US 6,555,880 B2.
Self-Aligned Silicide Process For Silicon Sidewall Source And Drain Contacts
Patent No.: US 6,645,861 B2.
Self-Aligned Silicide Process For Reduction Of Si Consumption In Shallow Junction And Thin SOI Electronic Devices
Patent No.: US 6,444,578 B1.
Method For Increasing The Capacitance Of A Semiconductor Capacitor
Patent No.: US 6,358,813 B1.